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STT	Nội dung
1	Cross-Layer Modeling and Simulation of Circuit Reliability / Yu Cao and others
2	Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics / Yen-Lung Chen and others
3	Optimizing the Power Delivery Network in a Smartphone Platform / Woojoo Lee and others
4	Adaptive Energy Management for Dynamically Reconﬁgurable Processors / Muhammad Shaﬁque, Lars Bauer, Jorg Henkel
5	An Integrated Framework Toward Defect-Tolerant Logic Implementation onto Nanocrossbars / Yehua Su and Wenjing Rao
6	A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection / Chip-Hong Chang, Li Zhang
7	Optimized Micro-Channel Design for Stacked 3-D-ICs / Bing Shi, Ankur Srivastava
8	Algorithms for Maze Routing With Exact Matching Constraints / Muhammet Mustafa Ozdal, Renato Fernandes Hentschke
9	Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems / En-Jui Chang and others
10	Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing / Yi-Hua Li and others
11	A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Veriﬁcation / Bo-Han Wu, Chun-Ju Yang, and Chung-Yang (Ric) Huang
12	Debugging RTL Using Structural Dominance / Hratch Mangassarian, Bao Le and Andreas Veneris
13	Erratum to “Test Time Reduction in EDT Bandwidth Management for SoC Designs” / From p.168-172